Semiconductor device technologies continue to evolve, providing higher chip density and operating frequencies. Fin-type field-effect transistors (FinFETs) are one type of transistor technology that is currently used to help provide desired device scaling while maintaining appropriate power consumption budgets.
A fin-type field effect transistor is a transistor that is formed with a fin of material. A fin is a relatively narrow width and relatively tall height structure that protrudes from the top surface of a semiconductor layer. The fin width is intentionally kept small to limit the short channel effect.
In a conventional FinFET, a gate conductor is positioned on the top surface of the semiconductor layer and over a portion of the fin. The gate conductor runs parallel to the top of the semiconductor layer and is perpendicular to the fin length that the gate conductor intersects a portion of the fin. An insulator e.g., gate oxide) separates the gate conductor from the fin. Further, the region of the fin that is positioned below the gate conductor defines a semiconductor channel region. The FinFET structure can include multiple fins, in which case the gate conductor would wrap around, as well as fill in, the space between these fins. When the gate surrounds all sides of the fins, the resulting FinFET structure includes an all around gate and is commonly referred to as a nano-wire device.
When forming a FinFET structure or semiconductor device that includes an all around gate, a silicon on insulator (SOI) substrate is typically used. U.S. published patent application no. 2012/0138886, for example, discloses silicon and silicon germanium nano-wire devices. To form the nano-wire device, alternating layers of epitaxial silicon are formed on epitaxial silicon germanium on a SOI substrate, the alternating layers are patterned to form fin structures, and spacers are formed across and on the fin structures. A portion of the fin structures from source/drain regions on the substrate is removed. Source/drain structures are formed on the source/drain regions, wherein the source/drain regions are adjacent the spacers. One of the silicon and the epitaxial silicon germanium layers is removed from the fin structures disposed between the spacers.
As another example, U.S. published patent application no. 2008/013949 discloses a method of forming a stacked silicon-germanium nano-wire device on an SOI support substrate. The method includes forming a stacked structure on the SOI support substrate, with the stacked structure comprising at least one channel layer and at least one interchannel layer deposited on the channel layer. A fin structure is formed from the stacked structure. The fin structure includes at least two supporting portions and a fin portion arranged therebetween. The method further includes oxidizing the fin portion of the fin structure thereby forming the silicon-germanium nano-wire being surrounded by a layer of oxide, and removing the layer of oxide to form the silicon-germanium nano-wire. Nonetheless, there is still a need for other approaches to form semiconductor devices with all around gates.